A semiconductor memory device has a test mode for testing a normal operation before an end product is placed on the market. The testing is typically performed to determine whether there is a problem in an operation of a semiconductor memory device so that semiconductor memory devices capable of normal operation can be sorted as a good product. Such a test is performed as a semiconductor memory device enters a test mode, and a test result is monitored to determine whether the semiconductor memory device is operating normally.
FIG. 1 is a block diagram showing the configuration of a conventional semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device includes a test circuit 1 configured to receive a test enable signal TMEN which is enabled upon entry into a test mode and generate test mode signals TM<1:2> which are selectively enabled according to the test mode. The semiconductor memory device may also include an internal circuit 2 configured to perform a test according to a combination of the test mode signals TM<1:2>.
In such a semiconductor memory device, an operation error of the internal circuit 2 can be checked through a test result after performing the test. Cases where the operation error of the internal circuit 2 is checked include a case where a failure occurs during the test of the internal circuit 2 after entry into the test mode, and a case where a failures occurs because the levels of the test mode signals are not properly generated and thus it is impossible to enter the test mode. In this regard, there is no way to distinguish these two cases from each other by checking only the operation error of the internal circuit 2.